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W948D6FB / W948D2FB
256Mb Mobile LPDDR
4. PIN DESCRIPTION
4.1 Signal Descriptions
SIGNAL NAME
TYPE
FUNCTION
DESCRIPTION
Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE
A[n:0]
Input
Address
commands, to select one location out of the memory array in the
respective bank. The address inputs also provide the opcode
during a MODE REGISTER SET command.
A10 is used for Auto Pre-charge Select.
BA0, BA1
DQ0~DQ15 (×16)
DQ0~DQ31 (×32)
Input
I/O
Bank Select
Data Input/
Output
Define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Data bus: Input / Output.
CS enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS is
CS
Input
Chip Select
registered HIGH. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the
command code.
RAS
Input
Row Address
Strobe
RAS , CAS and WE (along with CS ) define the command
being entered.
CAS
Input
Column Address Referred to RAS
Strobe
WE
Input
Write Enable
Referred to RAS
Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
UDM / LDM(x16);
DM0 to DM3 (x32)
Input
Input Mask
DQS. Although DM pins are input-only, the DM loading matches
the DQ and DQS loading.
x16: LDM: DQ0 - DQ7, UDM: DQ8 – DQ15
x32: DM0: DQ0 - DQ7, DM1: DQ8 – DQ15,
DM2: DQ16 – DQ23, DM3: DQ24 – DQ31
CK and CK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of
CK / CK
Input
Clock Inputs
CK and negative edge of CK .Input and output data is referenced
to the crossing of CK and CK (both directions of crossing).
Internal clock signals are derived from CK/ CK .
Publication Release Date : Oct, 15, 2012
-6-
Revision : A01-004
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